1. Field of the Invention
The present invention relates to a structure of a power MOS transistor having a trench gate.
2. Discussion of the Background
FIG. 1 is a plan view showing a spline-structured MOS transistor manufactured based on current product design rules. Trench gates 45 and source contacts 46 are alternately formed on a semiconductor substrate. Each of the source contacts 46 is connected to a source electrode formed on a layer formed further thereon.
FIG. 2 is an upper surface view showing a pattern of an offset mesh-structured MOS transistor manufactured based on current product design rules. Trench gates 38 and source contacts 44 are alternately formed on a semiconductor substrate. Each of the source contacts 44 is connected to a source electrode formed on a layer formed further thereon. The offset mesh type is designed to realize a high degree of integration by forming transistors in longitudinal and lateral directions. In this MOSFET, an arraying ratio of the trench gates 38 and the source contacts 44 is set at 1:1. In other words, one trench gate and one source contact constitute one MOSFET.
FIG. 3 is a detailed sectional view of the MOS transistor shown in FIG. 2, taken along the lines 6—6 shown in FIG. 2. Now, the structure of this section will be described, as well as a method of manufacturing a semiconductor device including such structure.
First, as shown in FIG. 3, an N-type epitaxial layer 32 is formed on, for example an N+ type semiconductor substrate 31. On the surface of this epitaxial layer 32, a double diffused layer composed of a P-type base diffused layer 33 and an N+ type source diffused layer 34 is formed. Then, after an SiO film is formed on the source diffused layer 34, the resultant structure is subjected to patterning by a resist. Using this as a mask, the SiO film is punched. The resist is removed, and then using the SiO film as a mask, a trench 35 is formed to a depth punching through the base diffused layer 33. Subsequently, a gate insulating film 36 is formed on a full surface, and a polysilicon film 37 for a gate electrode is formed on the gate insulating film 36. Then, the polysilicon film 37 is removed until the surface of the gate insulating film 36 is exposed, and a trench gate 38 is formed.
Subsequently, to separate the trench gate 38 from the source contact, an interlayer film 39 is formed on a full surface. Using a resist (not shown) formed on the interlayer film 39 and then patterned, the interlayer film 39 is removed, and a contact hole 40 is formed to a depth punching through the source diffused layer 34. Then, impurity ions are implanted by using the interlayer film 39 as a mask, and a P+ type diffused layer 41 is formed in the bottom portion of the contact hole 40 inside the base diffused layer 33. Subsequently, a barrier metal layer 42 is formed on the full surface. An aluminum film 43 is formed on this barrier metal layer 42, and a source contact 44 is formed.
FIG. 4 is a sectional view showing a flow passage of a current when a voltage is applied to the MOS transistor shown in FIG. 3. When a drain voltage is applied to the semiconductor substrate 31, a channel region 45 is formed from the semiconductor substrate 31 to near the side face of the trench gate 38. A current flows from a drain through the channel region 45 to the diffused layer 34. The diffused layer 34 becomes a source region.
In this case, an increase in a channel density of the channel region 45 facilitates the flow of a current, making it possible to reduce the device resistance of the MOSFET.
Accordingly, to increase the number of channel regions 45, the number of trench gates 38, at the side faces of which channel regions 45 are formed, may be increased within a given region.
However, an increase in the number of trench gates 38 necessitates an increase in the number of source contacts 44. If a spacing between the trench gate 38 and the source contact 44 is small, shifting occurs in matching during a photo engraving process (PEP). An extra gate and source spacing must be provided for the trench gate 38 and the source contact 44. However, if an unexpected increase in the number of source pitches reduces the gate and source spacing, a reduction also occurs in the amount of margin between the gate and the source, resulting in a short-circuit failure therebetween.
Furthermore, if an opening of the source contact 44 is reduced, and the number of source pitches is increased in a given region, an aspect ratio of the contact hole 40 is increased, resulting in the impossibility of sufficient formation of the barrier metal layer 42 on the side face of the contact hole 40. The insufficient formation of the layer 42 causes reaction between the aluminum of the aluminum film 43 and the silicon of the substrate, which in turn generates aluminum spikes. Thus, because of improper formation of a depletion layer, current leakage occurs between the drain and the source.